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altima communications inc. ac108 rm/ru/rn ultra low power 10/100 bridge repeater general description the ac108r is a family of fully integrated multi port dual speed hubs with support for an sram interface, a single mii port, both 10m and 100m cascadable buses, stacking capability and snmp and rmon statistics. AC108RM ? 8 port, management, stack ac108ru ? 8 port, no management, stack ac108rn ? 8 port, no management, no stack ac108r products are fully compliant ieee 802.3(u) class ii repeaters. the device provides 8 ports of 10 base-t/100 base-tx interface. all ports support either auto-negotiation (aneg), parallel detection or selected media when configure accordingly. port 7 supports 100base-fx fiber media via pecl interfaces. the mii interface can be connected to any mii compliant mac at either 10m or 100m. once a port?s technology is set, the port automatically connects to one of the two internal repeaters, one operating at 10 mbps and the other one at 100 mbps. two integrated back-planes, one operating at 10 mbps and one at 100 mbps, allow port expansion up to 288 ports. an internal two port switch connects either the 10m and 100m repeater segments, or the 100m segment with an isolated port 7. external sram is used for address table and packet buffering. 64 and 32-bit snmp and rmon management counters are accessible via a high-speed serial management bus. features 8 10/100 tx or 7 10/100tx and 1 100fx ports embedded tx phys half duplex fefi on 100fx 10m or 100m mii for mac connection very small package - 272pbga 729 sq. mm footprint very low power - typ < 3w (total) selectable tx drivers for 1:1 or 1.25:1 transformers allowing for additional power reduction cable detect mode - typ < 1.4w (total) power down mode - typ < 1w (total) fully compliant with ieee 802.3 / 802.3u mii hdlc management bus (rmon/snmp) unh test labs (future) stackable to 288 ports non-blocking 10/100m bridge with mac controller and switching engine sram support as the external buffer memory up to 512k x 16. unique, per port, scrambler seed for reduced emissions baseline wander compensation highly efficient led outputs cable length indicator reverse polarity detection and correction with settable register bit indication 8 interrupts per port block diagram mac port 1 eeprom access control led display control 10/100 segment switching logic AC108RM/ru/rn phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100/fx mii stack i/f 100tx repeater fifo ctrl 10bt repeater stack i/f fifo ctrl sram controller serial i/f mac port 0 address management !0/100 stacking control bridge mib mgt counter AC108RM only AC108RM/ru only
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 2 of 55 general description ................................ ................................ ................................ ................................ ................................ .......... 1 features ................................ ................................ ................................ ................................ ................................ .............................. 1 block diagram ................................ ................................ ................................ ................................ ................................ .................. 1 pin diagram - AC108RM/ru/rn ................................ ................................ ................................ ................................ ................. 5 pin descriptions ................................ ................................ ................................ ................................ ................................ ................ 6 mdi (media dependent interface) pins (tx) ................................ ................................ ................................ ..................... 6 mdi (media dependent interface) pins (fx) ................................ ................................ ................................ ..................... 7 mii (media independent interface) pins ................................ ................................ ................................ ............................. 7 serial configuration prom ................................ ................................ ................................ ................................ ...................... 7 100mbps stacked bus for back-plane (stack master mode) ................................ ................................ ........................... 8 100mbps internal repeater bus ................................ ................................ ................................ ................................ ............ 8 10mbps stacked bus for back-plane (stack master mode) ................................ ................................ ............................. 9 10mbps internal repeater bus ................................ ................................ ................................ ................................ .............. 9 serial management port ................................ ................................ ................................ ................................ ....................... 10 led display ................................ ................................ ................................ ................................ ................................ ........... 10 control and setup ................................ ................................ ................................ ................................ ................................ .. 11 clock, reset & misc. ................................ ................................ ................................ ................................ ............................ 11 sram interface ................................ ................................ ................................ ................................ ................................ ..... 12 power and ground ................................ ................................ ................................ ................................ ................................ . 13 functional description ................................ ................................ ................................ ................................ ................................ ... 14 mac interface ................................ ................................ ................................ ................................ ................................ ................. 14 mii ................................ ................................ ................................ ................................ ................................ ................................ 14 smi ................................ ................................ ................................ ................................ ................................ ........................... 14 interrupt ................................ ................................ ................................ ................................ ................................ ................... 14 carrier sense / rx_dv ................................ ................................ ................................ ................................ ......................... 15 media interface ................................ ................................ ................................ ................................ ................................ ............... 15 10base-t ................................ ................................ ................................ ................................ ................................ ...................... 15 transmit function ................................ ................................ ................................ ................................ ................................ . 15 receive function ................................ ................................ ................................ ................................ ................................ ... 15 link monitor ................................ ................................ ................................ ................................ ................................ .......... 15 100base-tx ................................ ................................ ................................ ................................ ................................ ................. 15 transmit function ................................ ................................ ................................ ................................ ................................ . 15 parallel to serial, nrz to nrzi, and mlt3 conversion ................................ ................................ ............................. 16 receive function ................................ ................................ ................................ ................................ ................................ ... 16 baseline wander compensation ................................ ................................ ................................ ................................ ......... 16 clock/data recovery ................................ ................................ ................................ ................................ ............................ 16 decoder/de-scrambler ................................ ................................ ................................ ................................ .......................... 17 link monitor ................................ ................................ ................................ ................................ ................................ .......... 17 100base-fx ................................ ................................ ................................ ................................ ................................ ................. 17 transmit function ................................ ................................ ................................ ................................ ................................ . 17 receive function ................................ ................................ ................................ ................................ ................................ ... 17 link monitor ................................ ................................ ................................ ................................ ................................ .......... 17 far-end-fault-insertion (fefi) ................................ ................................ ................................ ................................ ........... 17 10base-t/100base-tx/fx ................................ ................................ ................................ ................................ ....................... 18 multi-mode transmit driver ................................ ................................ ................................ ................................ ............... 18 adaptive equalizer ................................ ................................ ................................ ................................ ................................ 18 pll clock synthesizer ................................ ................................ ................................ ................................ ......................... 18 jabber and sqe (heartbeat) ................................ ................................ ................................ ................................ ................ 18 reverse polarity detection and correction ................................ ................................ ................................ ....................... 18 inter-repeater interface ................................ ................................ ................................ ................................ ................................ . 19 10m internal repeater bus ................................ ................................ ................................ ................................ ....................... 19
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 3 of 55 100m internal repeater bus ................................ ................................ ................................ ................................ .................... 19 initialization and setup ................................ ................................ ................................ ................................ ................................ .. 19 hardware configuration ................................ ................................ ................................ ................................ ............................ 19 software configuration ................................ ................................ ................................ ................................ ............................. 19 leds ................................ ................................ ................................ ................................ ................................ ............................. 19 auto-negotiation ................................ ................................ ................................ ................................ ................................ ....... 19 parallel detection ................................ ................................ ................................ ................................ ................................ ....... 20 diagnostics ................................ ................................ ................................ ................................ ................................ .................. 20 loopback operation ................................ ................................ ................................ ................................ .............................. 20 cable length indicator ................................ ................................ ................................ ................................ ......................... 21 reset and power ................................ ................................ ................................ ................................ ................................ .............. 21 clock ................................ ................................ ................................ ................................ ................................ ................................ . 21 bridge function ................................ ................................ ................................ ................................ ................................ .... 21 buffer interface ................................ ................................ ................................ ................................ ................................ ........... 21 forwarding scheme ................................ ................................ ................................ ................................ ................................ ... 21 address recognition ................................ ................................ ................................ ................................ ................................ . 22 network management ................................ ................................ ................................ ................................ ............................... 22 media access control ................................ ................................ ................................ ................................ ............................... 22 buffer management ................................ ................................ ................................ ................................ ................................ ... 22 buffer allocation ................................ ................................ ................................ ................................ ................................ ............ 22 register descriptions ................................ ................................ ................................ ................................ ................................ ..... 23 global registers ................................ ................................ ................................ ................................ ................................ ......... 27 repeater mib ................................ ................................ ................................ ................................ ................................ ......... 27 100xcvr counters ................................ ................................ ................................ ................................ .............................. 28 rmon statistic counter ................................ ................................ ................................ ................................ ...................... 28 port n last new address registers ................................ ................................ ................................ ................................ .... 28 port n authorized address registers ................................ ................................ ................................ ................................ . 29 search address registers ................................ ................................ ................................ ................................ ..................... 29 port status registers ................................ ................................ ................................ ................................ ............................. 29 port enable control register ................................ ................................ ................................ ................................ ............... 30 interrupt registers ................................ ................................ ................................ ................................ ................................ . 30 repeater configuration register ................................ ................................ ................................ ................................ ......... 31 miscellaneous registers ................................ ................................ ................................ ................................ ....................... 32 bridge configuration register 1 ................................ ................................ ................................ ................................ ......... 32 bridge configuration register 2 ................................ ................................ ................................ ................................ ......... 32 led effect with port enable event. ................................ ................................ ................................ ................................ .. 32 led effect with partition/isolation event. ................................ ................................ ................................ ....................... 33 led effect with link event. ................................ ................................ ................................ ................................ ............... 33 led effect with activity (crs) event. ................................ ................................ ................................ ............................ 33 led effect with auto-negotiating event. ................................ ................................ ................................ ........................ 34 led effect with speed100 event. ................................ ................................ ................................ ................................ ...... 34 led register control mode. ................................ ................................ ................................ ................................ ............... 34 phy registers ................................ ................................ ................................ ................................ ................................ ............ 35 control register ................................ ................................ ................................ ................................ ................................ ..... 35 status register ................................ ................................ ................................ ................................ ................................ ....... 36 phy identifier 1 register ................................ ................................ ................................ ................................ ..................... 36 phy identifier 2 register ................................ ................................ ................................ ................................ ..................... 36 auto-negotiation advertisement register ................................ ................................ ................................ ........................ 37 auto-negotiation link partner ability register ................................ ................................ ................................ .............. 37 auto-negotiation expansion register ................................ ................................ ................................ ............................... 37 auto-negotiation next page transmit register ................................ ................................ ................................ .............. 38 extended control register ................................ ................................ ................................ ................................ ................... 38 auto-negotiation test register. ................................ ................................ ................................ ................................ ......... 39
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 4 of 55 receive error counter ................................ ................................ ................................ ................................ .......................... 39 eeprom table ................................ ................................ ................................ ................................ ................................ .............. 40 4b/5b code-group table ................................ ................................ ................................ ................................ ............................. 41 electrical characteristics ................................ ................................ ................................ ................................ ....... 42 absolute maximum ratings ................................ ................................ ................................ ................................ .................... 42 operating range ................................ ................................ ................................ ................................ ................................ ......... 42 total power consumption ................................ ................................ ................................ ................................ ................... 42 ttl i/o characteristics ................................ ................................ ................................ ................................ ........................ 42 refclk and xtal pins ................................ ................................ ................................ ................................ .................... 43 i/o characteristics ? led/cfg pins ................................ ................................ ................................ ................................ . 43 100 base-tx transceiver characteristics ................................ ................................ ................................ ...................... 43 10 base-t transceiver characteristics ................................ ................................ ................................ ........................... 44 digital timing characteristics ................................ ................................ ................................ ................................ ..................... 45 power on reset ................................ ................................ ................................ ................................ ................................ ...... 45 management data interface ................................ ................................ ................................ ................................ ................. 45 100base-tx/fx mii transmit system timing ................................ ................................ ................................ ............... 46 100base-tx/fx mii receive system timing ................................ ................................ ................................ ................. 46 10base-t mii transmit system timing ................................ ................................ ................................ ............................ 47 10base-t mii receive system timing ................................ ................................ ................................ ............................. 48 100mbps internal / stacked repeater bus receive / transmit system timing ................................ ......................... 50 10mbps internal / stacked repeater bus receive / transmit system timing ................................ ........................... 50 sram read cycle ................................ ................................ ................................ ................................ ................................ 51 sram write cycle ................................ ................................ ................................ ................................ ............................... 52 sram write cycle ................................ ................................ ................................ ................................ ............................... 53 tx application termination ................................ ................................ ................................ ................................ ........................ 53 fx application termination ................................ ................................ ................................ ................................ ......................... 55
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 5 of 55 pin diagram - AC108RM/ru/rn bottom view : - standard i/o - ground - digital vcc - analog vcc - g/t ? 0.75 + 0.15(272x) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 27.00 + 0.20 0.56 1.17 0.60 + 0.10 2.33 + 0.13 1.27 24.13 27.00 + 0.20 1.27 24.13 a b c d e f g h j k l m n p r t u v w y
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 6 of 55 pin descriptions many of the pins of these devices have multiple functions. the multi-function pins will be designated by bolding of the pin number. the separate descriptions of these pins will be listed in the proper sections. designers must assure that they have identified all modes of operation prior to final design. notes: the pin assignment shown below and in the pin description table is subjected to change without notice. the user is advised to contact altima communications inc. before implement any design based on the information provided in this data sheet. signals types: ?i? = input ?o? = output ?z? = high impedance ?u? = pull up with 10k ohm ?d? = pull down with 10k ohm ?a? = analog signal ?*? = active low signal mdi (media dependent interface) pins (tx) pin name bga # type description rxip_7 rxip_6 rxip_5 rxip_4 rxip_3 rxip_2 rxip_1 rxip_0 c19 f20 g19 k20 l19 n17 p19 t18 ai ai ai ai ai ai ai ai receiver input positive for both 10base-t and 100base-tx. rxin_7 rxin_6 rxin_5 rxin_4 rxin_3 rxin_2 rxin_1 rxin_0 c20 f19 g20 k19 l20 n18 p18 t19 ai ai ai ai ai ai ai ai receiver input negative for both 10base-t and 100base-tx. txop_7 txop_6 txop_5 txop_4 txop_3 txop_2 txop_1 txop_0 d20 e19 h20 j19 m19 p20 r19 r18 ao ao ao ao ao ao ao ao transmitter output positive for both 10base-t and 100base-tx. txon_7 txon_6 txon_5 txon_4 txon_3 txon_2 txon_1 txon_0 d19 e20 h19 j20 m20 n19 t20 r17 ao ao ao ao ao ao ao ao transmitter output negative for both 10base-t and 100base-tx.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 7 of 55 mdi (media dependent interface) pins (fx) pin name bga # type description fxip_7 a17 ai receiver input positive for 100base-fx . fxin_7 c17 ai receiver input negative for 100base-fx . fxop_7 c16 ao transmitter output positive for 100base-fx. fxon_7 b17 ao transmitter output negative for 100base-fx. sdp7 a18 ai fx signal detect positive . sdn7 a19 ai fx signal detect negative . mii (media independent interface) pins pin name bga # type description mii_txd3 mii_txd2 mii_txd1 mii_txd0 v16 w16 y16 v15 i,d mii transmit data. the mac will source txd[3:0] synchronous with mii_txclk when tx_en is asserted. mii_txclk w15 o mii transmit clock. continuous (25mhz/2.5mhz) clock output used by mac to synchronize mii_txen, mii_txd[3:0], and mii_txer. mii_txen u14 i,d mii transmit enable. indicates mac has presented valid data on the mii_txd[3:0]. mii_txer v14 i,d mii transmit error. indicates mac has presented invalid data on the mii_txd[3:0]. phy will generate error symbol /e/ on the wire. mii_rxd3 mii_rxd2 mii_rxd1 mii_rxd0 v13 w13 u12 v12 o mii receive data. the phy will source rxd[3:0] synchronous with mii_rxclk when rx_en is asserted. mii_rxclk w12 o mii transmit clock. continuous (25mhz/2.5mhz) clock output used by mac to synchronize mii_rxen, mii_rxd[3:0], and mii_rxer. mii_rxdv y12 o mii receive data-valid. phy has presented valid recovered on the mii_rxd[3:0]. mii_rxer v11 o mii receive error. indicates phy has received invalid symbol data. mii_crs w14 o mii carrier sense. active when carrier has been sensed. during full duplex mode, crs only responses to received carrier. mii_col y14 o mii collision detection. active when collision is detected. mii_spdsel u16 i,u mii port speed selection. 1 = 100 mb. 0 = 10 mb. serial configuration prom pin name bga # type description prom_cs b11 o prom chip select. (for use with 93c46 serial eeprom) prom_clk c13 o prom clock. prom_out a13 o prom data out. prom_in b12 i,d prom data in.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 8 of 55 100mbps stacked bus for back-plane (stack master mode) pin name bga # type description 100crsu_in* d3 i,u 100m carrier sense up in. active when carrier is sensed from upper stacks. only chipid 00 needs to be connected. 100crsd_in* c2 i,u 100m carrier sense down in. active when carrier is sensed from lower stacks. only chipid 00 needs to be connected. 100crsu_out* d2 o,z 100m carrier sense up out. active when receive activity detected on the current stack. this pin is to be daisy chained with upper stack. the last stack can leave this pin unconnected. 100crsd_out* b1 o,z 100m carrier sense down out. active when receive activity detected on the current stack. this pin is to be daisy chained with lower stack. the last stack can leave this pin unconnected. 100colbp* c1 i,o 100m collision. active when collision is detected. all 100colbp* pins on the stack must be tied together. 150 ohm pull up to 3.3v on first stack. this pin is monitored to detect collisions on other devices. 100crsbp* c3 i,o,u 100 carrier sense backplane. active when crs is detected. all 100crsbp* pins on the stack must be tied together. this pin is monitored to detect crs on other devices. 100oe* a1 o 100m output-enable. control pin to enable an external buffer. 100dir d4 o 100m direction. control pin for the direction of an external buffer. 0=input (default), 1=output. 100mbps internal repeater bus pin name bga # type description m100col_local* j1 i/o,z,u 100m local collisions. input on chipid 00. active low to indicate collision on all other chipids. m100acto* j3 i/o,u output to chipid 00 to signal local activity. (see next 3 signals) m100acti_0* j3 i/o,u connected from chipid 00 to chipid 01 m100acto* to sense activities. open on all other chipids. m100acti_1* j2 o,u connected from chipid 00 to chipid 10 m100acto* to sense activities. open on all other chipids. m100acti_2* k3 o,u connected from chipid 00 to chipid 11 m100acto* to sense activities. open on all other chipids. m100col_sys* h1 i/o,u chipid 00 will drive this pin the same as 100colbp* to indicate local collision. m100crs_sys* k2 i/o,u chipid 00 will drive this pin the same as 100crsbp* to indicate local activity. ms100d4 ms100d3 ms100d2 ms100d1 ms100d0 h4 g1 g2 g3 g4 i/o i/o i/o i/o i/o multiple/stacked data group. transmit and receive data in de- scrambled 5b data groups for multiple devices. data is sampled at the rising edge of ms100d_clk and driven out on falling edge of ms100d_clk. ms100d_en* h2 i/o,u multiple/stacked data enable. active when data is valid. ms100d_clk h3 i/o multiple/stacked data clock the bi-directional non-continuous 25 mhz recovered clock for synchronizing with ms100d[4:0], & ms100d_en*.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 9 of 55 10mbps stacked bus for back-plane (stack master mode) pin name bga # type description 10crsu_in* e2 i,u 10m carrier sense up in. active when carrier is sensed from upper stacks. only chipid 00 needs to be connected. 10crsd_in* e1 i,u 10m carrier sense down in. active when carrier is sensed from lower stacks. only chipid 00 needs to be connected. 10crsu_out* d1 o,z 10m carrier sense up out. active when receive activity detected on the current stack. this pin is to be daisy chained with upper stack. the last stack can leave this pin unconnected. 10crsd_out* f4 o,z 10m carrier sense down out. active when receive activity detected on the current stack. this pin is to be daisy chained with lower stack. the last stack can leave this pin unconnected. 10colbp* e3 i/o 10m collision. active when collision is detected. all 10colbp* pins on the stack must be tied together. 330 ohm pull up to 3.3v on first stack. this pin is monitored to detect collisions on other devices. 10crsbp* f3 i/o,u 10 carrier sense backplane. active when crs is detected. all 100crsbp* pins on the stack must be tied together. this pin is monitored to detect crs on other devices. 10oe* f1 o 10m output-enable. control pin to enable an external buffer. 10dir f2 o 10m direction. control pin for the direction of an external buffer. 0=input (default), 1=output. 10mbps internal repeater bus pin name bga # type description m10col_local* m1 i/o,z, u 100m local collisions. input on chipid 00. active low to indicate collision on all other chipids. m10acto* m2 i/o,u output to chipid 00 to signal local activity. (see next 3 signals) m10acti_0* m2 i/ o,u connected from chipid 00 to chipid 01 m10acto* to sense activities. open on all other chipids. m10acti_1* m3 o,u connected from chipid 00 to chipid 10 m10acto* to sense activities. open on all other chipids. m10acti_2* m4 o,u connected from chipid 00 to chipid 11 m10acto* to sense activities. open on all other chipids. m10col_sys* l3 i/o,u chip id 00 will drive this pin the same as 10colbp* to indicate local collision. m10crs_sys* n1 i/o,u chip id 00 will drive this pin the same as 10crsbp* to indicate local activity. ms10d l1 i/o multiple/stacked data group. transmit and receive data in 10bt for multiple devices. data is sampled at the rising edge of ms10d_clk and driven out on falling edge of ms10d_clk . ms10d_en* l2 i/o,u multiple/stacked data enable. active when data is valid. ms10d_clk k1 i/o multiple/stacked data clock the bi-directional non-continuous 10 mhz recovered clock for synchronizing with ms10d, & ms10d_en*.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 10 of 55 serial management port pin name bga # type description reconfig a7 i,d re-arbitration. when this pin toggles (0-1-0), "requestid" will be sent to agent to restart arbitration to get a new hubid. ser_match b7 o active high output indicated serial address match occurred. srx c7 i serial receive is sampled on the rising edge of serclk stx d7 o,z serial transmit is driven on the falling edge of serclk. when not driven, it is tri-stated. serclk a6 i clock for serial management interface. arbin b6 i daisy chain arbitration input this signal requires a 10k ohms pulled low. arbout c6 o daisy chain arbitration output. default high upon power up. int* d5 o interrupt. mgr_pres* c5 i,u manager present. led display pin name bga # type description led_ln7 led_ln6 led_ln5 led_ln4 led_ln3 led_ln2 led_ln1 led_ln0 a9 b9 c9 a10 b10 a11 d11 a12 o enable corresponding led display line in the display matrix, active low output. the detail of how to program and connect the leds is in the led setup section. led_data7 led_data6 led_data5 led_data4 led_data3 led_data2 led_data1 led_data0 b12 c13 a13 b13 b14 d14 a15 b15 i/o,d output for led display information of each column in the display matrix. active high output. the led pins are shared with reset-read configuration pins, test pins and eeprom interface. the value applied on the reset-read pins is only valid at the end of the reset cycle. the eeprom interface is active after the reset cycle. once the data in the eeprom is read the same pins are used for led display.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 11 of 55 control and setup pin name bga # type description mode[0] mode[1] b15 a15 i,d mode 1 - mode 0 domain "a" domain "b" 0 0 10m rptr 100m rptr (master) 0 1 10m rptr 100m rptr (stand alone) 1 0 port 7 100m rptr 1 1 illegal configuration. pulled up or down through 10k ohm resistor. chipid[0] chipid[1] d14 b14 i,d to assign chip id for 4 devices in a single box. one and only one device in the box must be assigned with chipid=0. pulled up or down through 10k ohm resistor. ibref a16 i reference bias resistor. connected to analog ground through a 10k (1%) resistor. fx_sel7 b13 i, d select fx mode for port 7. 0=tx, 1=fx clock, reset & misc. pin name bga # type description reset* n2 i,u reset to initial and defaulted state. clk p4 i 25mhz-system-clock reference input. this pin shall be connected to an external 25mhz-clock source. multiple devices should be synchronous to the same external clock source. ramtest[0] ramtest[1] y6 w6 i/o,d read during reset. 00 = normal mode, no ram test 01 = reserved 10 = reserved 11 = normal mode, ram test
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 12 of 55 sram interface the sram interface is designed to support low cost 2*32k*8 or 2*64k*8 asynchronous memory. pin name bga # type description ce0* n3 o chip enable for sram 0 chip. ce0* is inverted from ce1*. ce1* n4 o chip enable for sram 1 chip. ce1* is inverted from ce0*. gw* p1 o global write, active low signal. oe* p2 o output enable, active low signal. ram_size[1] ram_size[0] y7 w7 i/o,u external sram size per chip, read during reset. 00 = 128k x2 - 01 = invalid - 10 = 256k x2 - 11 = 512k x2 rama_17 rama_16 rama_15 rama_14 rama_13 rama_12 rama_11 rama_10 rama_9 rama_8 rama_7 rama_6 rama_5 rama_4 rama_3 rama_2 rama_1 rama_0 w11 y11 y10 u10 y9 w9 v9 y8 w8 y7 w7 v7 y6 w6 v6 u6 v5 y4 i/o sram address output. ramd_15 ramd_14 ramd_13 ramd_12 ramd_11 ramd_10 ramd_9 ramd_8 ramd_7 ramd_6 ramd_5 ramd_4 ramd_3 ramd_2 ramd_1 ramd_0 w4 u5 v4 v3 w1 v2 v1 u3 u2 u1 t4 t3 t2 t1 r3 r2 i/o,d sram data input and output
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 13 of 55 power and ground pin name bga # type description power 1 a8,a14 b8 d6,d10,d13,d16 e4 h17 j4 k17 l4 m17 r4 u7,u9,u11,u13 v10 w10 y13 vccd digital vcc total of 21 digital vcc pins. power 2 c8,c10,c12,c14 f17-18 h18 k18 m18 p17 vcca analog vcc total of 10 digital vcc pins. ground a2-5,a20 b2-5,b18-20 c4,c11,c18 d8,d9,d12,d17,d18 e17-18 g17-18 j9-12, j17-18 k4,k9-12 l9-12,l17-18 m9-12 n20 p3 r1,r20 t17 u4,u8,u15,u17-20 v8,v18-20 w2-3,w5,w18-20 y1-3,y5,y15,y17,y19-20 gnd ground total of 75 ground pins. n/c b16, c15, d15, v17, w17, y18 n/c total of 6 no connect pins
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 14 of 55 functional description the ac108r is a single chip 10/100mbps repeater controller with bridge function. the device provides 8 10base-t/100base-tx twisted pair interface ports supporting aneg, parallel detection and force media operation. upon technology selection, each port is logically attached to either the internal 10mbps repeater or the internal 100mbps repeater. all ports running at the same speed will repeat among themselves. 10m and 100m stacking buses are available to allow port expansion up to 288 ports in one collision domain at each speed on the ac108r . in addition to the two internal repeaters the ac108r includes a built-in 2-segment switch for connection between the 10m and the 100m repeater segments, or between the 100m repeater and an isolated port 7, depending on the setting of the mode[1:0] bits. snmp and rmon statistic can be gathered through a high speed hdlc serial management interface for intelligent hub applications. the ac108r?s ultra low power architecture consumes ~1a maximum @ 3.3volts when all ports are running 100base-tx full speed. a built-in power management function will power down the individual ports when no cable is detected which helps further drive down the power consumption and improve long-term reliability. functions: 4b/5b mlt3 nrzi manchester encoding and decoding clock and data recovery stream cipher scrambling / de-scrambling adaptive equalization line transmission carrier sense link integrity monitor auto-negotiation (aneg)/parallel detection 10mbps and 100mbps repeating 2 port switching mii mac connection hdlc management interface snmp/rmon statistics tables mac interface mii the media independent interface (mii) is an 18 wire mac/phy interface described in 802.3u. the purpose of the interface is to allow mac layer devices to attach to a variety of physical layer devices through a common interface. mii operates at either 100mbps or 10mbps, dependant on the speed of the physical layer. with clocks running at either 25 mhz or 2.5 mhz, 4 bit data is clocked between the mac and phy, synchronous with enable and error signals. mii data is received from and transmitted to the internal repeater determined by the mii_spdsel pin. on receipt of valid data from the wire interface, rx_dv will go active signaling to the mac that the valid data will be presented on the rxd[3:0] pins at the speed of the rx_clk. on transmission of data from the mac, tx_en is presented to the phy indicating the presence of valid data on txd[3:0]. txd[3:0] are sampled by the phy synchronous to tx_clk during the time that tx_en is valid. smi the serial management interface (smi) provides system access to the snmp, rmon and port status registers of the device. a single, daisy chain connection can be use to read and/or write the registers of multiple devices. the interface consists of two digital signals; clock and data. hdlc formatted packets, with a start/stop flag, header and crc field for error checking, are use for all reads and writes. zero-bit insertion/removal is used. operation speed can range from 0 to 2 mbps. interrupt the intr pin on the phy will be asserted whenever one of 8 selectable interrupt events occur. assertion state is programmable to either high or low through the intr_levl register bit. selection is made by setting the appropriate bit in the interrupt mask register. when the intr bit goes active, the mac
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 15 of 55 interface is required to read the interrupt status register to determine which event caused the interrupt. the status bits are read only and clear on read. when intr is not asserted, the pin is held in a high impedance state. carrier sense / rx_dv carrier sense is asserted asynchronously on the crs pins as soon as activity is detected on the receive data stream of any port connected to the repeater to which the mii is connected. rx_dv is asserted as soon as a valid ssd (start-of-stream delimiter) is detected. carrier sense and rx_dv are de-asserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. however, if the carrier sense is asserted and a valid ssd is not detected immediately, rx_er is asserted instead of rx_dv. in 10base-t mode, crs is asserted asynchronously when the valid preamble and data ac tivity is detected on the rxip and rxin pins. since the device is always in half duplex mode, the crs is activated during both the transmission and reception of data. media interface 10base-t when configured to run in 10base-t mode, either through hardware configuration, software configuration or aneg , the phy will support all the features and parameters of the industry standards. transmit function parallel to serial logic is used to convert the 4-bit (mii) data into the serial stream. the serialized data goes directly to the manchester encoder where it is synthesized through the output waveshaping driver. the waveshaper reduces any emi emission by filtering out the harmonics, therefore eliminating the need for an external filter. receive function the received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. this eliminates the need for a 10base-t external filter. a manchester decoder converts the incoming serial stream. serial to parallel logic is used to generate the 4-bit (mii) data. link monitor the 10-base-t link-pulse detection circuit will constantly monitor the rxip/rxin pins for the presence of valid link pulses. in the absence of valid link pules, the link status bit will be cleared and the link led will de-assert. 100base-tx when configured to run in 100base-tx mode, either through hardware configuration, software configuration or aneg , the phy will support all the features and parameters of the industry standards. transmit function in 100base-tx mode, the phy transmit function converts synchronous 4-bit (mii) data to a pair of 125 mbps differential serial data streams. the serial data is transmitted over network twisted pair cables via an isolation transformer. data conversion includes 4b/5b encoding, scrambling, parallel to serial, nrz to nrzi, and mlt-3 encoding. the entire operation is synchronous to 25 mhz and 125 mhz clock. both clocks are generated by an on-chip pll clock synthesizer that is locked on to an exter nal 25 mhz clock source. the transmit data is transmitted from the mac to the phy via the txd[3:0] signals. the 4b/5b encoder replaces the first two nibbles of the preamble from the mac frame with a /j/k/ code-group pair start-of- stream delimiter (ssd), following the onset of tx_en signal. the 4b/5b encoder appends a /t/r/ code-group pair end-of-stream delimiter (esd) to the end of transmission in place of the first two idle code-groups that follow the negation of the tx_en signal. the encapsulated data stream is converted from 4-bit nibbles to 5-bit code-groups. during the inter-packet gap, when there is no data present, a continuous stream of idle code-groups are transmitted. when tx_er is asserted while tx_en is active, the transmit error code-group /h/ is substi- tuted for the translated 5b code word. the 4b/5b encoding is bypassed when scramble disable is set. in 100base-tx mode, the 5-bit transmit data stream is scrambled as defined by the tp-pmd stream cipher function in order to reduce radiated emissions on the twisted pair cable. the scrambler en codes a
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 16 of 55 plain text nrz bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: x[n] = x[n-11] + x[n-9] (modulo 2) the scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted fre- quency range, thus eliminating peaks at any single frequency. for repeater applications, where all ports transmit the same data simultaneously, signal energy is spread further by using a non-repeating sequence for each phy, i.e., the scrambled seed is unique for each different phy based on the phy address. parallel to serial, nrz to nrzi, and mlt3 conversion the 5-bit nrz data is clocked into phy?s shift register with a 25 mhz clock, and clocked out with a 125 mhz clock to convert it into a serial bit stream. the serial data is convert ed from nrz to nrzi format, which produces a transition on logic 1 and no transition on logic 0. to further reduce emi emissions, the nrzi data is converted to an mlt-3 signal. the conversion offers a 3db to 6db reduction in emi emissions. this allows system designers to meet the fcc class b limit. whenever there is a transition occurring in nrzi data, there is a corresponding transition occurring in the mlt-3 data. for nrzi data, it changes the count up/down direction after every single transition. for mlt-3 data, it changes the count up/down direction after every two transitions. the nrzi to mlt-3 data conversion is implemented without reference to the bit timing or clock information. the conversion requires detecting the transitions of the incoming nrzi data and setting the count up/down direction for the mlt-3 data. asserting fx_sel high will disable this encoding. receive function the 100base-tx receive path functions as the inverse of the trans mit path. the receive path includes a receiver with adaptive equalization and dc restoration in the front end. it also includes a mlt-3 to nrzi con verter, 125 mhz data and clock recovery, nrzi/nrz conversion, serial-to-parallel conversion, de-scrambler, and 5b/4b decoder. the receiver circuit starts with a dc bias for the differential rx+/- inputs, followed with a low-pass filter to filter out high frequency noise from the transmission channel media. an energy detect circuit is also added to determine whether there is any signal energy on the media. this is useful in the power- saving mode. the amplification ratio and slicer?s threshold is set by the on-chip bandgap reference. baseline wander compensation the 100base-tx data stream is not always dc balanced. the transformer blocks the dc components of the incoming signal, thus the dc offset of the differential re ceive inputs can drift. the shifting of the signal level, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion. this creates jitter and possible increase in the bit error rates. therefore, a dc restoration circuit is needed to compensate for the attenuation of the dc component. this phy implements a patent-pending dc restoration circuit. unlike the traditional implementation, the circuit does not need the feedback information from the slicer or the clock recovery circuit. this design simplifies the circuit design and eliminates any random/systematic offset on the receive path. in the 10baset and the 100base- fx modes, the baseline wander correction circuit is not required, and therefore is disabled. clock/data recovery the equalized mlt-3 signal passes through the slicer circuit, and gets converted to nrzi for mat. the phy uses a proprietary mixed-signal phase locked loop (pll) to extract clock information from the in coming nrzi data. the extracted clock is used to re-time the data stream and set the data boundaries. the transmit clock is locked to the 25 mhz clock input while the receive clock is locked to the in coming data streams. when initial lock is achieved, the pll switches to the data stream, extracts the 125 mhz clock, and uses it for the bit framing for the recovered data. the recovered 125 mhz clock is also used to generate the 25 mhz mii_rxclk (mii). the pll re quires no external components for its operation and has high noise immunity and low jitter. it pro vides fast phase alignment and locks to data in one transition. its data/clock acquisition time after power-on is less than 60 transitions. the pll can maintain lock on run- lengths of up to 60 data bits in the absence of signal transitions. when no valid data is present, i.e. when the sd is de-asserted, the pll will switch and lock on to mii_txclk. this provides a continuously running mii_rxclk (mii). at the pcs interface, the 5 bit data rxd[4:0] is synchronized to the 25 mhz rx_clk.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 17 of 55 decoder/de-scrambler the de-scrambler detects the state of the transmit linear feedback shift register (lfsr) by looking for a sequence representing consecutive idle codes. the de-scrambler acquires lock on the data stream by recognizing idle bursts of 30 or more bits and locks its frequency to its de-ciphering lfsr. once lock is acquired, the device can operate with an inter-packet-gap (ipg) as low as 40 ns. however, before lock is acquired, the de-scrambler needs a minimum of 270 ns of consecutive idles in between packets in order to acquire lock. the de-ciphering logic also tracks the number of consecutive errors received while the rx_dv is asserted. once the error counter exceeds its limit currently set to 64 consecutive errors, the logic as- sumes that the lock has been lost, and the de-cipher circuit resets itself. the process of regaining lock will start again. stream cipher de-scrambler is not used in the 100base-fx and the 10base-t modes. link monitor signal level is detected through a squelch detection circuitry. a signal detect (sd) circuit allows the equal izer to assert high whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mv. this is approximately 40% of a normal signal voltage level. in addition, the energy level must be sustained for longer than 2~3 m s in order for the signal detect signal to stay on. the sd gets de-asserted approximately 1~2 m s after the energy level drops consistently below 300 mv from peak to ground. the link signal is forced low during a local loopback operation (loopback register bit is set) and forced to high when a remote loopback is taking place (en_rpbk is set). in forced 100base-tx mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor enters in the ?link fail? state and nlp's are transmitted. when a valid signal is detected for a minimum period of time, the link monitor enters link pass state and transmits mlt-3 signal. 100base-fx when port 7 is configured to run in 100base-fx mode, either through hardware configuration or software configuration (100base-fx does not support aneg ) the phy will support all the features and parameters of the industry standards. transmit function the serialized data bypasses the scrambler and 4b/5b encoder in fx mode. the output data is nrzi pecl signals. the pecl level signals are used to drive the fiber-transmitter. receive function in 100base-fx mode, signal is received through the pecl receiver inputs, and directly passed to the clock recovery circuit for data/clock extraction. in fx mode, the scrambler/de-scrambler cipher function is bypassed. link monitor in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the phy?s sdp pin. far-end-fault-insertion (fefi) aneg provides the mechanism to inform the link partner that a remote fault has occurred. however, aneg is disabled in the 100base-fx applications. an alternative in-band signaling function (fefi) is used to signal a remote fault condition. fefi is a stream of 84 consecutive ones followed by one logic zero. this pattern is repeated 3 times. a fefi will signal under 3 conditions: when no activity is received from the link partner when the clock recovery circuit detects a signal error or pll lock error when management entity sets the transmit far- end-fault bit. the fefi mechanism is enabled by default in the 100base-fx mode, and is disabled in 100base-tx or 10base-t modes. the register setting can be changed by software after reset.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 18 of 55 10base-t/100base-tx/fx multi-mode transmit driver the multi-mode driver transmits the mlt-3 coded signal in 100base-tx mode, nrzi coded sig nal in 100base-fx mode, and manchester coded signal in 10base-t mode. in 100base-fx mode, no filtering is performed. the transmit driver utilizes a current drive output which is well balanced and produces a low noise pecl signal. pecl voltage levels are pro duced with resistive terminations. in 10baset mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external filter. the flp and nlp pulses are also drive out through the 10baset driver. the 10baset and 100basetx transmit signals are multiplexed to the trans mit output driver. t his arrangement results in using the same external transformer for both the 10baset and the 100basetx. the driver output level is set by a built- in bandgap reference and an external resistor connected to the ribb pin. the resistor sets the output current for all modes of operation. the txop/n outputs are open drain devices with a serial source to i/o pad resistance of 10 w max. when the 1:1 transformer is used, the current rating is 40 ma for the 2v p-p mlt-3 signal, and 100 ma for the 5v p-p manchester signal. one can use a 1.25:1 transmit transformer for a 20% output driver power reduction. this will decrease the drive current to 32 ma for 100base-tx operation, and 80 ma for 10base-t operation. adaptive equalizer the phy is designed to accommodate a maximum of 150 meters utp cat-5 cable. an at&t 1061 cat- 5 cable of this length typically has an attenuation of 31 db at 100 mhz. a typical attenuation of 100- meter cable is 21 db. the worst case cable attenuation is around 24-26 db as defined by tp- pmd specification. the amplitude and phase distortion from the cable cause inter-symbol interference (isi) which makes clock and data recovery difficult. the adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable. the equalizer has the ability to changes its equalizer frequen cy response according to the cable length. the equalizer will tune itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. pll clock synthesizer the phy includes an on-chip pll clock synthesizer that generate 25 mhz and 125 mhz clocks for the 100base-tx circuitry. it also generates 20 mhz and 100 mhz clocks for the 10baset and aneg circuitry. the pll clock generator uses a fully differential vco cell that introduces very low jitter. the zero dead zone phase detection method implemented in the phy design provides excellent phase track ing. a charge pump with charge sharing compensation is also included to further reduce jitter at different loop filter voltages. the on-chip loop filter eliminates the need for external components and minimizes the external noise sensitivity. only one external 25 mhz clock source is required as a reference clock. after power-on or reset, the pll clock synthesizer generates the 20 mhz clock output until the 100base-x operation mode is selected. jabber and sqe (heartbeat) after the mac transmitter exceeds the jabber timer (46ms), the transmit and loopback functions will be disabled and col signal get asserted. after tx_en goes low for more than 500 ms, the tp transmitter will reactivate and col gets de-asserted. set ting jabber disable will disable the jabber function. when the sqe test is enabled, a col pulse with 5- 15bt is asserted after each transmitted packet. sqe is enabled in 10base-t by default, and can be disabled via sqe test inhibit. reverse polarity detection and correction certain cable plants have crossed wiring on the twisted pairs; the reversal of txin and txip. under normal circumstances this would cause the receive circuitry to reject all data. when the auto polarity disable bit is cleared, the phy has the ability to detect the fact that either 8 nlps or a burst of flps are inverted and automatically reverse the receiver?s polarity. the polarity state is stored in the reverse polarity bit.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 19 of 55 if the auto polarity disable bit is set, then the reverse polarity bit can be written to force the polarity reversal of the receiver. inter-repeater interface two busses are provided to allow connection between multiple ac108rs, or combinations of ac108rs and ac105s . the two busses connect directly to the internal repeaters, one at 10m and one at 100m. all necessary csma/cd parameters are met on the internal repeater busses. in addition to the internal repeater busses, both 10m and 100m data can be transferred between multiple boxes in a stacked configuration. at power on, reset and stack change times, configuration of multiple devices occurs. 10m internal repeater bus up to 4 ac108rs can be configured to run within a single box. chip id's are selected through external pins. 100m internal repeater bus initialization and setup hardware configuration several different states of operation can be chosen through hardware configuration. external pins may be pulled either high or low at reset time. the combination of high and low values determines the power on state of the device. many of these pins are multi-function pins which change their meaning when reset ends. software configuration several different states of operation can be chosen through software configuration. please refer to the smi section as well as the register descriptions . leds the ac108rx has an intricate, yet efficient led scheme allowing up to 64 different led outputs while only using 16 i/o pins on an 8 x 8 matrix. 8 of the i/o pins, labeled led_data[0:7] drive a single pulse on a consistently timed interval. these 8 signals are the enable signals for the leds. the other 8 i/o pins, labeled led_ln[0:7] drive the actual led information on the line. when an led_ln[n] signal is true during the period that the corresponding led_data[n] signal is active, then the led will light. in all other cases, the led will not light. the information contained in led_ln[0:2] is programmable (see register descriptions.) the default state of these outputs is as follows: led_ln[7] ? alert coditions led_data[7] ? utilization domain a led_data[6] ? utilization domain b led_data[5] ? collision domain a led_data[4] ? collision domain b led_data[3] ? memory domain a led_data[2] ? memory domain b led_data[1] ? partition domain a led_data[0] ? partition domain b led_ln[6] ? collision histogram domain a led_ln[5] ? collision histogram domain a led_ln[4] ? utilization histogram domain b led_ln[3] ? utilization histogram domain a led_ln[2] ? programmable synchronous to led_data[n] led_ln[1] ?- port speed / partition synchronous to led_data[n] led_ln[0] ? port link / activity synchronous to led_data[n] the histogram features allow an 8-segment bar graph led to be attached to the corresponding outputs to show the utilization percentage of the specified condition. collision histogram 66% 32% 16% 8% 4% 2% 1% 1 event utilization histogram 80% 66% 32% 16% 8% 4% 2% 1% auto-negotiation the 10/100 transceiver is able to run at either 10mbps over twisted pair copper (10base-t), 100mpbs over twisted pair copper (100base-tx) or 100mpbs over fiber optics (100base-fx) (port 7 only). because the phy sections are all attached to
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 20 of 55 the internal repeaters, they will only advertise and operate in half duplex mode. to determine the operational state, the phy has hardware selects and software selects while also supporting auto- negotiation and parallel detection. to run in 100base-fx mode, the selection must be done through hardware configuration. there is no support for auto-negotiation of the fx interface. legitimate operating states are: 10base-t half duplex 100base-tx half duplex 100base-fx half duplex (port 7 only) the phy can be hardware configured to force any one of the above mentioned modes. by forcing the mode, the phy will only run in that mode, hence limiting the locations where the product will operate. the phy is able to negotiate its mode of operation in the twisted pair environment using the auto- negotiation mechanism defined in the clause 28 of ieee 802.3u specification. aneg can be enabled or disabled by hardware or software control. when the aneg is enabled, the phy chooses its mode of operation by advertising its abilities and comparing them with the ability received from its link partner. it can be configured to ad vertise 100base-tx or 10base-t operating in half duplex. the auto-negotiation advertisement register contains the current capabilities of each phy, determined through hardware selects or chip defaults. this information is sent to its link partner during the aneg process using fast link pulses (flps). an flp is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a link code word. after reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. therefore, the hardware has priority over software. when aneg is enabled, the phy sends out flps during the following conditions: power on link loss restart aneg command during this period, the phy continually sends out flps while monitoring the incoming flps from the link partner to determine their optimal mode of operation. if flps are not detected during this phase of operation, parallel detection mode is entered (see below). when the phy receives 3 identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words, sets the acknowledge bit in the generated flps, and waits to receive 3 identical code word with the acknowledge bit set from the link partner. once this occurs the phy configures itself to the highest technology that is common to both ends. the technology priorities are: 1. 100base-tx, half-duplex 2. 10base-t half-duplex. once the aneg is complete, auto-negotiate complete is set, the status register reflects negotiated speed, and the phy enters the negotiated transmission and reception state. this state will not change until link is lost or the phy is reset through either hardware or software, or the restart negotiation bit (reg. 0.9) is set. parallel detection because there are many devices in the field that do not support the aneg process, but must still be communicated with, it is necessary to detect and link through the parallel detection process. the parallel detection circuit is enabled in the absence of flps. the circuit is able to detect: normal link pulse (nlp) 10base-t receive data 100base-tx idle the mode of operation gets configured based on the technology of the incoming signal. if any of the above is detected, the device automatically configures to match the detected operating speed in the half duplex mode. this ability allows the device to communicate with the legacy 10base-t and 100base-tx systems, while maintaining the flexibility of auto-negotiation. diagnostics loopback operation local loopback and remote loopback are provided for testing purpose. they can be enabled through software. the local loopback routes transmitted data through the transmit path back to the receiving path?s clock and data recovery module. the loopback data are presented to the pcs in 5 bits symbol format. this loopback is used to check the operation of the 5-bit
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 21 of 55 symbol decoder and the phase locked loop circuitry. in local loopback, the sd output is forced to logic one and txop/n outputs are tri-stated. in remote loopback, incoming data is passed through the equalizer and clock recovery, then looped back to the nrzi/mlt3 converter and then to the transmit driver. this loopback is used to ensure the device?s connection on the media side. it also checks the operation of the device's internal adaptive equalizer, phase locked loop circuit, and wave-shaper synthesizer. during remote loopback, signal detect (sd) output is forced to logic zero. cable length indicator the phy can detect the length of the cable it?s attached and display the result in reg. 20.[7:4]. a reading of [0000] translates to < 10m cable used, [0001] translates to ~ 10 meter of cable, and [1111] translates to 150 meter cable. the cable length value can be used by the network manage to determine the proper connectivity of the cable and to manage the cable plant distribution reset and power the phy can be reset in three ways: during initial power on. hardware reset: a logic low signal of 150 m s pulse width is applied to rst* pin. software reset: write to the control register. directly following reset, the device will run a memory test on the external ram, and download its initial configuration from the eeprom. the power consumption of the device is significantly reduced due to its built-in power management features. separate power supply lines are used to power the 10baset circuitry and the 100basetx circuitry. therefore, the two circuits can be turned- on and turned-off independently. when the phy is set to operate in 100base-tx mode, the 10base-t circuitry is powered down, and vice versa. the following power management features are supported: 1. power down mode: this can be achieved by writing to the control register. during power down mode, the device is still be able to interface through the smi. 2. energy detect / power saving mode: energy detect mode turns off the power to select internal circuitry when there is no live network connected. energy detect (ed) circuit is always turned on to monitor if there is a signal energy present on the media. the smi circuitry is also powered on and ready to respond to any management transaction. the transmit circuit still send out link pulses with minimum power consumption. if a valid signal is received from the media, the device will power up and resume normal transmit/receive operation. (patent pending) 3. reduced transmit drive strength mode: additional power saving can be gained at the phy level by designing with 1.25:1 turns ration magnetic and asserting the tp125 pin at reset. clock the clock input must a ttl clock oscillator measured at 25 mhz-100ppm. bridge function buffer interface port b is always connected to 100 mb repeater core. port a of the bridge is connected to 10 mb repeater core in mode 00, or to port 7 in mode 01. two collision domain are called domain ?a?, and domain ?b? respectively. the switch engine interface presents an 18-bit address bus for memory access. the sram buffer for the two-port switch contains address look-up table and output data queue. the address look-up table consists of 1k entries, 2 layers with each entry occupies 8 words; totaling 8k words. the remaining memory is devoted to output data queueing. for buffer management, each packet occupies 1.5k, 1536 bytes. forwarding scheme the switch supports store-and-forward scheme only. it does not support cut-through-forward. with store-and-forward, the incoming packet must be completely received into the buffer without error before it can be forwarded.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 22 of 55 address recognition the self-learning bridge function is based on source address field of packets. the switch uses 2-layer look-up table and xor hashing. each port of the switch engine will read, store and compare the contents of the destination address (da) and the source address (sa) on all incoming packets. if the da matches a previously stored sa on the same port of the bridge, then the packet will not be forwarded. if the da does not match, then the packet will be forwarded to the other port of the bridge. all broadcast packet will be forwarded without comparison. too remove the possibility of the sa and da tables saturating, all entries are marked to be removed after a certain period of time. on reception of a packet on the same port with the same sa, the aging marker is revised. programmable aging time and fast aging control is supported. network management management statistics are maintained on a per port, per repeater and per switch basis. all management information will be retrieved through a simple hdlc interface. media access control the switch engine implements all functions of ieee 802.3 mac protocol such as frame formatting, collision handling, etc. it generates 56-bit preamble and start of frame delimiter while a packet is being sent. in half duplex mode, the switch will perform all required functions of csma/cd. buffer management the switch buffering management requires 1.5k, 1536 bytes, memory to store one packet. the buffer size of each port is decided by mode[1:0] and external ram size[1:0]. mode 10 sets both sides of bridge to 100m mode, therefore the buffer are made equal. in all other modes it is assumed that the low speed port will need more storage for outgoing packets. the switch uses the five pointers to control per port buffer status. start address is the beginning point of memory address for each port and end address point is the last entry. these two registers are determined at reset. the read/write pointers are dynamically changed depending on the current outgoing and incoming packets in the storage. if packet counter is equal to maximum number of the packets that can be stored, then the buffer is full and the packet is dropped. in all other occurrences, the packet is stored in the next available buffer. buffer allocation buffer allocation sram size[1:0] 00(128k) 01(256k) 10(512k) mode[1:0] 10 others 10 others 10 others lookup table 2k entries maximum packets for port 0 (ibqa) 80 100 165 200 336 400 maximum packets for port 1 (iaqb) 80 60 165 130 336 272 start read write point end address packet counter per port buffer management
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 23 of 55 register descriptions the internal register sets are listed below. each register contains 32-bit data. the addresses shown below are hexadecimal. bold definitions indicate a group heading, grayed definitions indicates the members of the bolded group. several bolded groups do not show the members because they are the same as a previously define group. descriptions of the individual registers follows this table. note: when writing to registers it is recommended that a read/modify/write operation be performed, as unintended bits may get set to unwanted states. this applies to all register, including those with reserved bits. note: for all registers define as sa5-sa4 and sa3-sa0 for the value 12-34-56-78-9a-bc: example: sa5-sa4 = xx-xx-bc-9a example: sa3-sa0 = 78-56-34-12 bank base addresss definition type 0 000 - 00f port 0 repeater mib 0 000 readable frame count r 0 001 readable byte count (lower) r 0 002 readable byte count (upper) r 0 003 crc count r 0 004 alignment error count r 0 005 long frame count r 0 006 short event count r 0 007 runt count r 0 008 collision count r 0 009 late event count r 0 00a very long event count r 0 00b data rate mismatch count r 0 00c auto partition count r 0 00d sa change count r 0 00e broadcast count r 0 00f multicast count r 0 010 - 01f port 1 repeater mib 0 020 - 02f port 2 repeater mib 0 030 - 03f port 3 repeater mib 0 040 - 04f mii port repeater mib 0 050 ? 058 100xcvr counters - port 0-3 050 port isolate ? port 0 r 051 port isolate ? port 1 r 052 port isolate ? port 2 r 053 port isolate ? port 3 r 055 symbol error - port 0 r 056 symbol error - port 1 r 057 symbol error - port 2 r 058 symbol error - port 3 r 0 05c - 06f rmon statistic counter - segment 0 0 05c byte count (lower) r 0 05d byte count (upper) r 0 05e packet count r 0 05f broadcast count r
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 24 of 55 bank base addresss definition type 0 060 multicast count r 0 061 crc alignment error count r 0 062 undersize pkt count r 0 063 oversize pkt count r 0 064 fragment count r 0 065 jabber count r 0 066 collision count r 0 067 64 byte pkt count r 0 068 65-127 byte pkt count r 0 069 128-255 byte pkt count r 0 06a 256-511 byte pkt count r 0 06b 512-1023 byte pkt count r 0 06c 1024-1522 byte pkt count r 0 06d not used 0 06e good byte count (lower) r 0 06f good byte count (upper)- r 0 070 port 0 last new sa3~sa0 r 0 071 port 0 last new sa5~sa4 r 0 072 port 1 last new sa3~sa0 r 0 073 port 1 last new sa5~sa4 r 0 074 port 2 last new sa3~sa0 r 0 075 port 2 last new sa5~sa4 r 0 076 port 3 last new sa3~sa0 r 0 077 port 3 last new sa5~sa4 r 0 078 mii port last new sa3~sa0 r 0 079 mii port last new sa5~sa4 r 0 080 port 0 authorized sa3~sa0 r/w 0 081 port 0 authorized sa5~sa4 r/w 0 082 port 1 authorized sa3~sa0 r/w 0 083 port 1 authorized sa5~sa4 r/w 0 084 port 2 authorized sa3~sa0 r/w 0 085 port 2 authorized sa5~sa4 r/w 0 086 port 4 authorized sa3~sa0 r/w 0 087 port 4 authorized sa5~sa4 r/w 0 088 mii port authorized sa3~sa0 r/w 0 089 mii port authorized sa5~sa4 r/w 0 08a search sa3~sa0 r/w 0 08b search sa5~sa4 r/w 0 090 search port match register r 0 095 port enable control register r/w 0 096 port authorized address learning control register r/w 0 098 port link status r 0 099 port polarity status r 0 09a port partition status r 0 09c port speed status r 0 09d port isolation status (fast ethernet only) r 0 09e port sa change status r 0 09f reserved r 0 0ab repeater configuration r/w
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 25 of 55 bank base addresss definition type 0 0ac repeater serial configuration r 0 0ad device/revision id r 0 0ae interrupt status r/w 0 0af interrupt mask r/w 0 0b4 mii port status r 0 0b5 repeater reset register r 0 0b6 software reset register r 0 0ba bridge configuration register 1 r/w 0 0bb bridge configuration register 2 r/w 0 0c0 ? 0df phy 0 registers 0 0c0 control register r/w 0 0c1 status register r/w 0 0c2 phy identifier 1 register r/w 0 0c3 phy identifier 2 register r/w 0 0c4 auto-neg advertisement register r/w 0 0c5 auto-neg link partner register r/w 0 0c6 auto-neg expansion register r/w 0 0c7 auto-neg next page register r/w 0 0d0 extended control register r/w 0 0d1 adaptation control register r/w 0 0d2 auto-neg test register r/w 0 0d3 reserved r/w 0 0d4 dlock drop counter register r/w 0 0d5 receive error counter register r/w 0 0d6 power management register r/w 0 0e0 ? 0ff phy 1 registers 0 100 ? 11f phy 2 registers 0 120 ? 13f phy 3 registers 0 140 ? 15f phy 4 registers 0 160 ? 17f phy 5 registers 0 190 eeprom address 1 0 191 eeprom address 2 0 1a0 ? 1bf phy 6 registers 0 1c0 ? 1df phy 7 registers 0 1e0 ? 1ef led effect register 0 1e0 reserved r 0 1e1 led effect with port enable event r 0 1e2 led effect with partition/isolation event r 0 1e3 led effect with link event r 0 1e4 led effect with activity (crs) event r 0 1e5 led effect with autoneg event r 0 1e6 led effect with speed100 event r 0 200 - 207 ether-like/bridge mib - segment 0 0 200 single col frame r 0 201 multiple col frame r 0 202 deferred transmission r 0 203 late col frame r 0 204 excessive col frame r 0 205 delay exceeded discard frame r
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 26 of 55 bank base addresss definition type 0 206 drop event count r 0 207 drop packet count r 0 300 ? 31f phy global register 1 000 - 00f port 4 repeater mib 1 010 - 01f port 5 repeater mib 1 020 - 02f port 6 repeater mib 1 030 - 03f port 7 repeater mib 1 040 - 04f not used 1 050 - 058 100xcvr counters - port 4-7 1 05c - 06f rmon statistic counter - segment 1 1 05c byte count(lower) r 1 05d byte count(upper) r 1 05e packet count r 1 05f broadcast count r 1 060 multicast count r 1 061 crc alignment error count r 1 062 undersize pkt count r 1 063 oversize pkt count r 1 064 fragment count r 1 065 jabber count r 1 066 collision count r 1 067 64 byte pkt count r 1 068 65-127 byte pkt count r 1 069 128-255 byte pkt count r 1 06a 256-511 byte pkt count r 1 06b 512-1023 byte pkt count r 1 06c 1024-1522 byte pkt count r 1 06d not used r 1 06e good byte count(lower) r 1 06f good byte count(upper)- r 1 070 port 4 last new sa3~sa0 r 1 071 port 4 last new sa5~sa4 r 1 072 port 5 last new sa3~sa0 r 1 073 port 5 last new sa5~sa4 r 1 074 port 6 last new sa3~sa0 r 1 075 port 6 last new sa5~sa4 r 1 076 port 7 last new sa3~sa0 r 1 077 port 7 last new sa5~sa4 r 1 078 - 079 not used 1 080 port 4 authorized sa3~sa0 r/w 1 081 port 4 authorized sa5~sa4 r/w 1 082 port 5 authorized sa3~sa0 r/w 1 083 port 5 authorized sa5~sa4 r/w 1 084 port 6 authorized sa3~sa0 r/w 1 085 port 6 authorized sa5~sa4 r/w 1 086 port 7 authorized sa3~sa0 r/w 1 087 port 7 authorized sa5~sa4 r/w 1 088 - 089 not used r/w
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 27 of 55 bank base addresss definition type 1 200 - 207 ether-like/bridge mib - segment 1 r 1 200 single col frame 1 201 multiple col frame 1 202 deferred transmission 1 203 late col frame 1 204 excessive col frame 1 205 delay exceeded discard frame 1 206 drop event count 1 207 drop packet count global registers repeater mib name description readable frame count counts valid (error free) packets. unicast-only (reg.0ab) = 0: counts all packets. unicast-only (reg.0ab ) = 1: counts unicast packets only. readable byte count (lower) counts the number of octets in all valid packets, not including preamble and framing bits. this counter is not affected by unicast-only bit. readable byte count (upper) crc count counts valid length , collision-free packets that had fcs error, but were correctly framed (had an integral number of octets). alignment error count counts valid length, collision-free packets that had fcs error and were incorrectly framed (had an non-integral number of octets). long frame count counts packets (good or bad) that had a length greater than 1518 octets. short event count counts events that lasted for less than shorteventmaxtime.. 100m : shorteventmaxtime = 84 bit times, 10m : shorteventmaxtime = 77 bit times. runt count counts events longer than shorteventmaxtime, but shorter than validpacketmintime; or packets longer than shorteventmaxtime, but octets less than 64 bytes. validpacketmintime = 560 bit times. collision count counts the number of collisions that occurred , including late collision. late event count counts the number of collision s detected after the lateev en tthreshold. 100m: lateeventthreshold = 484 bit times. 10m: lateeventthreshold = 500 bit times. very long event count counts events that lasted for longer than 4 to 7.5 ms. data rate mismatch count counts the number of times the incoming data rate mismatched the local clock source enough to cause a fifo underflow or overflow. auto partition count counts the number of times this port has been partitioned by the auto -partition algorithm. sa change count counts the number of times the source address has changed. broadcast count counts the number of good broadcast packets received by this port. multicast count counts the number of good multicast packets received by this port.
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 28 of 55 100xcvr counters name description port isolate ? port n counts the number of times a port auto isolates. port isolate ? port n port isolate ? port n port isolate ? port n symbol error - port n counts the number of time a packet contained at least one symbol error. symbol error - port n symbol error - port n symbol error - port n rmon statistic counter name description byte count(lower) the number of data octets including those in good and bad packets and octets in fcs fields, but does not include preamble or other framing bits. byte count(upper) packet count the number of packets received from the network, including good and bad packets. broadcast count the number of good broadcast packets received. multicast count the number of good multicast packets received. crc alignment error count the number of valid-length packets that ha d a bad frame check sequence. undersize pkt count the number of well-formed packets that were smaller than 64 octets. oversize pkt count the number of well-formed packets that were longer than 1518 octets. fragment count the number of ill-formed packets less than 64 octets. any event without a sfd (0-octet oacket, e.g., jamed packets caused by collision) will be count as a fragment, no matter how long it is. jabber count the number of ill-formed packets longer than 1518 octets. an ill-formed packet is one with fcs error. collision count the best estimate of the total number of collision on this interface. 64 byte pkt count the number of packets (good and bad) that were 64 octets long. 65-127 byte pkt count the number of packets (good and bad) that were 65 to 127 octets long. 128-255 byte pkt count the number of packets (good and bad) that were 128 to 255 octets long. 256-511 byte pkt count the number of packets (good and bad) that were 256 to 511 octets long. 512-1023 byte pkt count the number of packets (good and bad) that were 512 to 1023 octets long. 1024-1518 byte pkt count the number of packets (good and bad) that were 1024 to 1518 octets long. not used good byte count (lower) the total number of octets contained in valid frames received on this segment. good byte count (upper) port n last new address registers name description port n last new sa3~sa0 last received source address. port n last new sa5~sa4
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 29 of 55 port n authorized address registers name description port n authorized sa3~sa0 address comparison. (see port learn control register) port n authorized sa5~sa4 search address registers name description search sa3~sa0 address used for search function. default to 00-00-00-00-00-00 search sa5~sa4 search port match register bit 0-8 indicate which port matched the search address. 31:9 8 7 6 5 4 3 2 1 0 rsv mii port port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 port status registers name description port enable control register 1 = port enabled if pin mgr_pres_ is low during reset, all ports will be disabled until the management software re-enables them. otherwise, all ports will power on enabled. port link status 1= link good, default = 0 port polarity status 1= the polarity has been crossed, default = 0 port partition status 1= the port has been partitioned, default = 0 port speed status 1= 100m, 0:10m , default = 0 port isolation status (fast ethernet only) 1= port has been isolated, default = 0 port sa change status 1 = source address changed, defa ult = 0 reserved reserved mii port status bits 31:2 reserved bit 1 0=10m, 1=100m bit 0 1=phy mode (always 1)
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 30 of 55 port enable control register bit name description mode default 31 lfsr_test 1: reduce lfsr timer for jabber, partition. r/w 0 30:19 reserved r 0 18 rambist_stat us internal ssram bist result. 0=pass, 1=fail. r 0 17:16 auth_cntl9 mii port authorized address learning mode. r/w 00 15:14 auth_cntl8 port 7 authorized address learning mode. r/w 00 13:12 auth_cntl7 port 6 authorized address learning mode. r/w 00 11:10 auth_cntl6 port 5 authorized address learning mode. r/w 00 9:8 auth_cntl5 port 4 authorized address learning mode. r/w 00 7:6 auth_cntl4 port 3 authorized address learning mode. r/w 00 5:4 auth_cntl3 port 2 authorized address learning mode. r/w 00 3:2 auth_cntl2 port 1 authorized address learning mode. r/w 00 1:0 auth_cntl1 port 0 authorized address learning mode. 0 0 learn each new sa. 0 1 learn the first sa only, then change these two bits to ?10? thus locking down the address. 1 0 lock. hardware has locked down the address, only software can now write to this address. 1 1 reserved. r/w 00 interrupt registers name description interrupt status default = 0 interrupt mask 1= mask, 0=unmask 31 30 29:8 7 6 5 4 3 2 1 0 rsv sa match rsv far end fault rsv jabber isolation partition fcc sa change speed change
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 31 of 55 repeater configuration register bit name description mode default 31:15 reserved r/w n/a 14:13 mode 00 = stack master 8 port + bridge 01 = stand alone 8 port 10 = stand alone 7 port + bridge + 1 port. port 7 is connected to the bridge port in this mode. the other bridge port is connected to 100 segment. 11 = illegal configuration r/w mode pins 12 late enable 0 = enable late event counter. 1 = disable late event counter. 11 write clear enable 0 = causes interrupt status register, search port match register, and sa change status registers to auto-clear when read. 1 = requires that the appropriate register bit be written to be clear. this is done by writing a ? 1 ? to the bit(s) that are to be cleared. 10 mib enable 1 = enable statistics gathering, 0 = disable. 9 send t/r not function. r/w 0 8 isolate 100 1 = disable 100m stack signals and external backplane transceiver. 0 = enable. r/w 0 7 isolate 10 1 : disable 10m stack signals and external backplane transceiver. 0 : enable. r/w 1 6 unicast only changes the definition of readframes counter to count unicast packets only. 1 = counts unicast only . 0 = counts all packets . r/w 0 5 arbit input value as read from arbit input pin. r 0 4 reset mib counter writing a 1 will reset all mib counters , this bit will reset to ? 0 ? after all counters have been cleared. r/w 0 3 reserved r/w 0 2 reserved r n/a 1 100m repeater partition alternative 0 = un-partition a port only when data can be transmitted out from the port for 560 bit-time without a collision. 1 = un-partition a port when data can be either transmitted from the port or received from the port for 560 bit-time without a collision. r/w 0 0 10m repeater partition alternative 0 = un-partition a port when data can be either transmitted from the port or received from the port for 560 bit-time without a collision. 1 = un-partition a port only when data can be received from the port for 560 bit-time without a collision r/w 0
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 32 of 55 miscellaneous registers name description repeater serial configuration this 8-bit register holds user-defined data device/revision id repeater reset register any write to this register causes repeater logic reset. software reset register any write to this register is identical to hardware reset. eeprom address 1 bits 47:16 of eeprom serial number. eeprom address 2 bits 15:0 of eeprom serial number. bridge configuration register 1 bit name description mode default 31:15 reserved r/w n/a 10 disable switch 0 = enable, 1 = disable switch function r/w 0 9 disable aging 0 = enable, 1 = disable aging function r/w 0 8 fast aging enable 0 = 300 seconds per unit, 1 =6 seconds per unit r/w 0 7:0 aging timer this count times the seconds per unit equals aging timout. eg. 010h * 300 seconds per unit = 4800 seconds 010h * 6 seconds per unit = 96 seconds r/w 01h bridge configuration register 2 bit name description mode default 31:16 reserved r/w n/a 15:8 ipg timer1 10/100m segment ipg adjustment. bit 15 is the sign bit. when the value is 0, the ipg is set to 96bt. one unit will increase or decrease 1bt for sni mode and 4bt for mii mode. r/w 0 7:0 ipg timer0 10/100m segment ipg adjustment. bit 15 is the sign bit. when the value is 0, the ipg is set to 96bt. one unit will increase or decrease 1bt for sni mode and 4bt for mii mode. r/w 01h led effect with port enable event. bit name description mode default 15:12 blink rate [3:0] set the blink rate bits [3:0] rw 0000 11 reserved ro 0 10:8 led on with port enable event when port enable, turn on corresponding led 2:0. rw 011 7 reserved ro 0 6:4 led blink with port enable event when port enable, blink corresponding led 2:0. rw 011 3 reserved ro 0 2:0 led off with port enable event when port enable, turn off corresponding led 2:0. rw 000
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 33 of 55 led effect with partition/isolation event. bit name description mode default 15:12 blink rate [7:4] set the blink rate bits [7:4]. rw 0001 19 reserved ro 0 10:8 led on with part/iso event when partition/isolation, turn on corresponding led 2:0. rw 000 7 reserved ro 0 6:4 led blink with part/iso event when partition/isolation, blink corresponding led 2:0. rw 010 3 reserved ro 0 2:0 led off with part/iso event when partition/isolation, turn off corresponding led 2:0. rw 000 led effect with link event. bit name description mode default 15:11 reserved ro 00000 10:8 led on with link event when link up, turn on corresponding led 2:0. rw 011 7 reserved ro 0 6:4 led blink with link event when link up, blink corresponding led 2:0. rw 011 3 reserved ro 0 2:0 led off with link event when link up, turn off corresponding led 2:0. rw 000 led effect with activity (crs) event. bit name description mode default 15:11 reserved ro 00000 10:8 led on with activity event when activity, turn on corresponding led 2:0. rw 000 7 reserved ro 0 6:4 led blink with activity event when activity, blink corresponding led 2:0. rw 001 3 reserved ro 0 2:0 led off with activity event when activity, turn off corresponding led 2:0. rw 000
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 34 of 55 led effect with auto-negotiating event. bit name description mode default 15:11 reserved ro 00000 10:8 led on with auto-negotiating event when auto-negotiating, turn on corresponding led 2:0. rw 000 7 reserved ro 0 6:4 led blink with auto-negotiating event when auto-negotiating, blink corresponding led 2:0. rw 000 3 reserved ro 0 2:0 led off with auto-negotiating event when auto-negotiating, turn off corresponding led 2:0. rw 000 led effect with speed100 event. bit name description mode default 15:11 reserved ro 00000 10:8 led on with speed100 event when speed100, turn on corresponding led 2:0. rw 010 7 reserved ro 0 6:4 led blink with speed100 event when speed100, blink corresponding led 2:0. rw 000 3 reserved ro 0 2:0 led off with speed100 event when speed100, turn off corresponding led 2:0. rw 000 led register control mode. bit name description mode default 15:8 led data set value shown on the led_data [7:0]. rw 0 7:0 led column control which lane of the led_data should be turned on. rw 0
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 35 of 55 phy registers the following registers are defined for each phy port. the register addresses are offset addresses. the actual address has to be calculated with their base address. the base addresses of phy-0 to phy-7 are 0c0, 0e0, 100, 120, 140, 160, 1a0, and 1c0 respectively. all of the addresses are hexadecimal. control register bit name description mode default 15 reserved ro 0 14 loopback 1 = loopback mode, which internally loops the transmit to the receive, thus it will ignore all the activity on the cable media. 0 = normal operation. rw 0 13 speed select 1 = 100mbps 0 = 10mbps. this bit will be ignored if auto-negotiation is enabled. it will no longer reflect auto-negotiation result. rw 0 (port 7 depends on fxsel & mode) 12 auto-neg enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process. in force mode, speed is selected via bit 0.13. rw 1 (port 7 depends on fxsel & mode) 11 power down 1 = power down mode, which puts device in low-power stand-by mode, which only react to management transaction. 0 = normal operation. rw 0 10 isolate 1 = electrical isolation of phy from mii and cable medi a. 0 = normal operation. rw 0 9 restart auto- negotiation 1 = restart auto-negotiation process. 0 = normal operation. rw/ sc 0 8 duplex mode 1 = full duplex. 0 = half duplex. full duplex is not supported on this chip. it will no longer reflect auto-negotiation result. ro 0 7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of tx_en signal. 0 = disable col test. rw 0 6:0 reserved r0 000000
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 36 of 55 status register bit name description mode default 15 100base-t4 tied to zero indicates no 100baset4 capability. ro 0 14 100base-tx full duplex tied to zero indicates no 100basetx full duplex support. ro 0 13 100base-tx half duplex 1 = 100basetx with half duplex. 0 = no tx half-duplex ability. ro 1 12 10base-t full duplex tied to zero indicates no 10base-t full duplex support. ro 0 11 10base-t half duplex 1 = 10baset with half duplex. 0 = no 10baset half-duplex ability. ro 1 10:6 reserved ro 00000 5 auto-negotiate complete 1 = auto-negotiate process completed, indicates reg. 4, 5, 6 are valid. 0 = auto-negotiate process not completed. ro n/a 4 remote fault 1 = remote fault condition detected. 0 = no remote fault. after this bit is set, it will remain set until it is clear by reading register 1 via management interface. sc/lh n/a 3 auto-negotiate ability 1 = able to perform auto-negotiation function, its value is determined by anega pin. 0 = unable to perform auto-negotiation function. ro 1 2 link status 1 = link is established, however, if link fails, this bit will become cleared and remain cleared until register is read via management interface. 0 = link is down, or have been dropped. sc/ll 0 1 jabber detect 1 = jabber condition detect. 0 = no jabber condition detected. sc/lh 0 0 extended capability 1 = extended register capable. this bit is tied permanently to one. ro 1 phy identifier 1 register bit name description mode default 15:0 oui* assigned to the 3 rd through 18 th bits of the organizationally unique identifier (oui), respectively. ro 0022 (hex) phy identifier 2 register bit name description mode default 15:10 oui assigned to the 19 th through 24 th bits of the oui. ro 010101 9:4 model number six bit manufacturer?s model number; 101 is encoded as 010001. ro 011000 3:0 revision number four bits manufacturer?s revision number. 0001 stands for rev. a, etc. ro 0001
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 37 of 55 auto-negotiation advertisement register bit name description mode default 15 next page 1 = desire next page. 0 = next page is not desired. rw 0 14 acknowledge this bit will be set internally after receiving 3 consecutive and consistent flp bursts. ro 0 13 remote fault 1 = remote fault detected. 0 = no remote fault. rw 0 12:10 reserved for future technology. rw 000 9 100base-t4 tied to zero indicates no 100base-t4 support. ro 0 8 100base-tx full duplex 1 = 100basetx with full duplex. 0 = no 100basetx full duplex ability. ro 0 7 100base-tx 1 = 100basetx capable. 0 = no 100basetx capability. rw 1 6 10base-t full duplex 1 = 10mbps with full duplex. 0 = no 10mbps with full duplex capability. ro 0 5 10base-t 1 = 10mbps capable. 0 = no 10mbps capability. rw 1 4:0 selector field [00001] = ieee 802.3. ro 00001 auto-negotiation link partner ability register bit name description mode default 15:0 technology technology capability field, which indicates the technology capability of link partner. the bit definition is the same as reg. 4.15:0. ro 0001(h) auto-negotiation expansion register bit name description mode default 15:5 reserved ro 0000 0000 000 4 parallel detection fault 1 = fault detected by parallel detection logic. this is caused by unstable link, or concurrent link up condition. 0 = no fault detected by parallel detection logic. sc/lh 0 3 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 2 next page able ro 1 1 page received 1 = a new link code word has been received. the contains of the received link code word is located in register 5. sc/lh 0 0 link partner auto-negotiation able 1 = link partner is auto-negotiation able. 1 = link partner is not auto-negotiation able. ro 0
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 38 of 55 auto-negotiation next page transmit register bit name description mode default 15 np 1 = another next page is desired. rw 0 14 reserved ro 0 13 message page 1 = message page. 0 = un-formatted page. rw 1 12 ack2 acknowledge2. 1 = will comply with message. 0 = can not comply with message. rw 0 11 toggle 1 = previous value of transmitted link code word equal to 0. 0 = previous value of transmitted link code word equal to 1. ro n/a 10:0 code message/un-formatted code field. rw 0001 extended control register bit name description mode default 15 repeater 1 = repeater mode. crs only responds to receive activity. 0 = dte mode. rw 1 14 cim disable 1 = disable carrier integrity monitor function. default is 1 when autoneg is enable. once speed is set to 100mbps, this bit will be set to ?0?. rw 1 13 fef enable 1 = enable fef generation and detection. 0 = enable fef generation and detection. when fx is selected, fef should be enabled. otherwise, it should be disabled. rw 0 12 fx sel 1 = enable fx mode. 0 = disable fx mode. rw 0/port 7 depend on fxsel 11 tp125 1 = uses 1.25:1 transformer. 0 = uses 1:1 transformer. rw 0 10 sdn select 1 = select internal common voltage setting. 2 = select external common voltage setting. rw 0 9 scramble disable 1 = disable scramble. 0 = enable scramble. rw 0 8:0 reserved ro 0 0000 0000
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 39 of 55 auto-negotiation test register. bit name description mode default 15 lp loop back 1 = link pulse loop back mode. 0 = normal operation. rw 0 14 force send nlp 1 = force link control state machine to send nlp even in auto-negotiation mode. 0 = normal operation. rw 0 13 force bt link up 1 = force nlp link integrity state machine to link up state. 0 = normal operation. rw 0 12 force tx link up 1 = force link monitor to link up state. 0 = normal operation. rw 0 11:10 reserved ro 00 9 arb_speed 1 = auto-negotiation result is 100 tx. 2 = auto-negotiation result is 10 bt. ro depends on aneg result 8 arb_duplex 1 = auto-negotiation result is full duplex. 0 = auto-negotiation result is half-duplex. ro depends on aneg result 7:4 arbitration state high highest state of auto-negotiation state machine since reset or last read operation. sc/r o 0000 depends on aneg state 3:0 arbitration state low lowest state of auto-negotiation state machine since reset or last read operation. ss/r o 1111 depends on aneg state receive error counter bit name description mode default 15:0 receive error counter number of receive error event. ro 0000
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 40 of 55 eeprom table table of locations and information required for initial setup of bridge, repeater and transceiver. address description assign to? 0 first word 1 port enable reg 095 2 mii port authorized address learning mode. reg 096 3 port 0-7 authorized address learning mode. reg 096 4 initial repeater configuration registers reg 0ab 5 initial repeater serial configuration reg 0ac 6 bridge configuration register 1 reg 0ba 7 bridge configuration register 2 reg 0bb 8 reserved reg 0bf[17:9] 9 reserved reg 0bf[8:0] 10 initialize port 0 control register reg 0c0 11 initialize port 0 extended control register reg 0d0 12 initialize port 1 control register reg 0e0 13 initialize port 1 extended control register reg 0f0 14 initialize port 2 control register reg 100 15 initialize port 2 extended control register reg 110 16 initialize port 3 control register reg 120 17 initialize port 3 extended control register reg 130 18 initialize port 4 control register reg 140 19 initialize port 4 extended control register reg 150 20 initialize port 5 control register reg 160 21 initialize port 5 extended control register reg 170 22 initialize port 6 control register reg 1a0 23 initialize port 6 extended control register reg 1b0 24 initialize port 7 control register reg 1c0 25 initialize port 7 extended control register reg 1d0 26 test control register reg 1e0 27 led effect with port enable event reg 1e1 28 led effect with partition/isolation event reg 1e2 29 led effect with link event reg 1e3 30 led effect with activity (crs) event reg 1e4 31 led effect with autoneg event reg 1e5 32 led effect with speed100 event reg 1e6 33 bits 47:32 of eeprom serial number. reg 190[31:16] 34 bits 31:16 of eeprom serial number. reg 190[15:0] 34 bits 15:0 of eeprom serial number. reg 191[15:0]
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 41 of 55 4b/5b code-group table pcs code group[4:0] symbol name mii (txd/rxd [3:0]) description 11110 0 0000 data 0 01001 1 0001 data 1 10100 2 0010 data 2 10101 3 0011 data 3 01010 4 0100 data 4 01011 5 0101 data 5 01110 6 0110 data 6 01111 7 0111 data 7 10010 8 1000 data 8 10011 9 1001 data 9 10110 a 1010 data a 10111 b 1011 data b 11010 c 1100 data c 11011 d 1101 data d 11100 e 1110 data e 11101 f 1111 data f idle and control code 11111 i 0000 inter-packet idle; used as inter-stream fill code. 11000 j 0101 start of stream delimiter, part 1 of 2; always use in pair with k symbol. 10001 k 0101 start of stream delimiter, part 2 of 2; always use in pair with j symbol. 01101 t undefined end of stream delimiter, part 1 of 2; always use in pair with r symbol. 00111 r undefined end of stream delimiter, part 2 of 2; always use in pair with t symbol. invalid code 00100 h undefined transmit error; used to send halt code-group 00000 v undefined invalid code 00001 v undefined invalid code 00010 v undefined invalid code 00011 v undefined invalid code 00101 v undefined invalid code 00110 v undefined invalid code 01000 v undefined invalid code 01100 v undefined invalid code 10000 v undefined invalid code 11001 v undefined invalid code
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 42 of 55 electrical characteristics note: the following electrical characteristics are design goals rather than characterized numbers. absolute maximum ratings storage temperature............................... -55 o c to +150 o c vcc supply referenced to gnd............. -0.5v to +5.0v digital input voltage............................... -0.5v to vcc dc output voltage.................................. -0.5v to vcc operating range operating temperature(ta) ........................... 0 o c to +70 o c vcc supply voltage range(vcc) .................. 2.97v to 3.63v total power consumption parameter symbol conditions min typ max units supply current (per port) icc 10 base-t, idle 10 base-t, normal activity 100 base-tx 100 base-fx 10/100 base-tx, low power without cable power down 25 41 85 30 12 30 75 100 40 15 1 ma ma ma ma ma ma supply current (dual speed hub) icc mode 00 mode 01 mode 10 175 140 175 200 180 200 ma ma ma ttl i/o characteristics parameter symbol conditions min typ max units input voltage high vih 2.0 v input voltage low vil 0.8 v input current ii -10 10 ma output voltage high voh vcc-0.4 v output voltage low vol 0.4 v output current high ioh 8 ma output current low iol -8 ma input capacitance ci 10 pf output transition time 3.15v < vcc < 3.45v 5 ns tristate leakage current |ioz| 10 ua
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 43 of 55 refclk and xtal pins parameter symbol conditions min typ max units input voltage low vil 0.8 v input voltage high vih 2.0 v input clock frequency tolerance f 50 ppm input clock duty cycle tdc 40 60 % input capacitance cin 3.0 pf i/o characteristics ? led/cfg pins parameter symbol conditions min typ max units output low voltage vol 0.4 v output high voltage voh 2.4 v input current ii -8 8 ma output current io -10 10 ma 100 base-tx transceiver characteristics parameter symbol conditions min typ max units peak to peak differential output voltage vp note 1 1.9 2.0 2.1 v output voltage symmetry vss note 1 .98 1.02 mv signal rise/fall time trf note 1 3.0 5.0 ns rise/fall time symmetry trfs note 1 3 4 4 ns duty cycle distortion dcd 250 ps overshoot/undershoot vos 5 % output jitter scrambled idle 1.4 ns receive jitter tolerance 4 ns output current high ioh 1:1 transformer 40 ma output current high ioh 1.25:1 transformer 32 ma common mode input voltage 1.8 v common mode input current 10 ua differential input resistance 5 k w note 1: 50 w ( 1%) resistor to vcc on each output
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 44 of 55 10 base-t transceiver characteristics parameter symbol conditions min typ max units peak to peak differential output voltage vop note 1 4.5 5 5.5 v signal rise/fall time 1 4 ns output current sink 15 16 ma output current high ioh 1:1 transformer 100 ma output current high ioh 1.25:1 transformer 80 ma start of idle pulse width 300 350 ns output jitter 1.4 ns receive jitter tolerance 32 ns receive input impedance zin 3.6 k w differential squelch threshold vds 300 400 500 mv common mode rejection 25 v differential input resistance 25 k w note 1: 50 w ( 1%) resistor to vcc on each output
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 45 of 55 digital timing characteristics power on reset parameter sym conditions min typ max units rst* low period trst 150 - - m s configuration tconf 100 - - ns management data interface parameter sym conditions min typ max units mgt clock tmdcl - - - ns mgt clock tmdch - - - ns receive data setup trds setup on read cycle - - - ns receive data hold trdh hold on read cycle - - - ns transmit data delay ttdd delay on write cycle - - - ns power on reset timing trst rst* tconf all configuration pins ser_clk srx management data interface timing stx tmdcl tmdch trds trdh ttdd
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 46 of 55 100base-tx/fx mii transmit system timing parameter sym conditions min typ max units tx_clk period tck 39.998 40.000 40.002 ns tx_clk high period tckh 18.000 20.000 22.000 ns tx_clk low period tckl 18.000 20.000 22.000 ns tx_en to /j/ ttj - 40 180 ns tx_en sampled to crs tcsa rptr is logic low - 40 180 ns tx_en sampled to col tcla rptr is logic low - 40 180 ns !tx_en to /t/ ttt - 40 180 ns !tx_en sampled to !crs tcsd rptr is logic low - 40 180 ns !tx_en sampled to !col tcld rptr is logic low - 40 180 ns tx propagation delay ttj from txd[3:0] to txop/n(fxtp/n) - 40 180 ns txd[3:0], tx_en, tx_er setup ttxs from rising edge of tx_clk 10 - - ns txd[3:0], tx_en, tx_er hold ttxh from rising edge of tx_clk 0 - - ns !tx_en to tx_en ttx_tx 120 - - ns fxtp/n tx_clk tx_en txd[3:0] tx_er txop/n /j/ /t/ tck tckh tckl ttxs ttxh ttx _tx ttj ttt 100base-tx/fx mii transmit timing crs col ttcsa ttcsd ttcla ttcld start of packet end of packet
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 47 of 55 100base-tx/fx mii receive system timing parameter sym conditions min typ max units rx_clk period tck 39.998 40.000 40.002 ns rx_clk high period tckh 18.000 20.000 22.000 ns rx_clk low period tckl 18.000 20.000 22.000 ns /j/k to rx_dv assert trdva - 40 180 ns /j/k to crs assert trcsa - 40 180 ns /j/k to col assert trcla rptr is logic low - 40 180 ns /t/r to !rx_dv trdvd rptr is logic low - 40 180 ns /t/r to !crs trcsd rptr is logic low - 40 180 ns /t/r to !col trcld rptr is logic low - 40 180 ns rx propagation delay trdva from rxip/n(fxrp/n) to rxd[3:0] - 40 180 ns rxd[3:0], rx_dv, rx_er setup trxs from rising edge of rx_clk 10 - - ns rxd[3:0], rx_dv, rx_er hold trxh from rising edge of rx_clk 10 - - ns fxrp/n rx_clk rx_dv rxd[3:0] rx_er rxip/n /j/k /t/r tck tckh tckl trxs trxh trdva 100base-tx/fx mii receive timing crs col trcsa trcsd trcla trcld start of packet end of packet trdvd
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 48 of 55 10base-t mii transmit system timing parameter sym conditions min typ max units tx_clk period tck 399.98 400.00 400.02 ns tx_clk high period tckh 180.00 200.00 220.00 ns tx_clk low period tckl 180.00 200.00 220.00 ns tx_en to sop ttj 240 - 360 ns tx_en sampled to crs ttcsa rptr is logic low - - 130 ns tx_en sampled to col ttcla rptr is logic low - - 300 ns !tx_en to eop ttj 240 - 360 ns !tx_en sampled to !crs ttcsd rptr is logic low - - 130 ns !tx_en sampled to !col ttcld rptr is logic low - - 300 ns tx propagation delay ttj from txd[3:0] to txop/n 240 - 360 ns txd[3:0], tx_en, tx_er setup ttxs from rising edge of tx_clk 10 - - ns txd[3:0], tx_en, tx_er hold ttxh from rising edge of tx_clk 0 - - ns !tx_en to tx_en ttx_tx 300 - - ns ttx _tx 10base-t mii transmit timing crs tx_clk tx_en txd[3:0] tx_er txop/n col tck tckh tckl ttxs ttxh ttcsa ttcsd ttcla ttcld start of packet end of packet ttj ttj
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 49 of 55 10base-t mii receive system timing parameter sym conditions min typ max units rx_clk period tck 399.98 400.00 400.02 ns rx_clk high period tckh 180.00 200.00 220.00 ns rx_clk low period tckl 180.00 200.00 220.00 ns crs to rx_dv trdva 100 100 100 ns sop to crs trcsa 80 - 150 ns sop to col trcla rptr is logic low 80 - 150 ns eop to !rx_dv trdvd rptr is logic low 120 - 140 ns eop to !crs trcsd rptr is logic low 130 - 190 ns eop to !col trcld rptr is logic low 125 - 185 ns rx propagation delay trdva from rxip/n to rxd[3:0] 180 - 250 ns rxd[3:0], rx_dv, rx_er setup trxs from rising edge of rx_clk 16 - - ns rxd[3:0], rx_dv, rx_er hold trxh from rising edge of rx_clk 12 - - ns 10base-t mii receive timing crs rx_clk rx_dv rxd[3:0] rx_er col tck tckh tckl trxs trxh trcsd trdva trcsa trcla trcld start of packet end of packet trdvd rxip/n sop eop
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 50 of 55 100mbps internal / stacked repeater bus receive / transmit system timing parameter sym conditions min typ max units ms100d_clk period tck ns ms100d_clk high period tckh ns ms100d_clk low period tckl ns /j/k (sop) to control tjc ns /t/r (eop) to !control ttc ns control to ms100d_clk tcd ns ms100d[0:4] setup tds ns ms100d[0:4] hold tdh ns control to txop/n tclt ns !control to !txop/n tcht ns control is the combination of the following signals: 100crsu_in*, 100crsd_in*, 100crsu_out*, 100crsd_out*, 100colbp*, 100crsbp*, 100oe*, 100dir*, m100col_local*, m100act0*, m100act1_0*, m100act1_1*, m100act1_2*, m100col_sys*, m100crs_sys*, ms100d_en* different signals are valid due to different scenarios, but the active time is the same. rxip/n txop/n /j/ /t/ 100mbps i/srb receive / transmit timing start of packet tck tckh tckl ms100d_clk control* end of packet ms100d[0:4] tjc ttc tcd tds tdh tclt tcht
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 51 of 55 10mbps internal / stacked repeater bus receive / transmit system timing parameter sym conditions min typ max units ms10d_clk period tck ns ms10d_clk high period tckh ns ms10d_clk low period tckl ns /j/k (sop) to control tjc ns /t/r (eop) to !control ttc ns control to ms10d_clk tcd ns ms10d[0:4] setup tds ns ms10d[0:4] hold tdh ns control to txop/n tclt ns !control to !txop/n tcht ns control is the combination of the following signals: 10crsu_in*, 10crsd_in*, 10crsu_out*, 10crsd_out*, 10colbp*, 10crsbp*, 10oe*, 10dir*, m10col_local*, m10act0*, m10act1_0*, m10act1_1*, m10act1_2*, m10col_sys*, m10crs_sys*, ms10d_en* different signals are valid due to different scenarios, but the active time is the same. 10mbps i/srb receive / transmit timing start of packet tck tckh tckl ms10d_clk control* end of packet ms10d[0:4] tjc ttc tcd tds tdh tclt tcht rxip/n sop eop txop/n
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 52 of 55 sram read cycle parameter sym conditions min typ max units read cycle trc 15 - ns address - oe valid tav - 15 ns output hold toh 3 - ns oe* access toea - 6 ns oe* to low z toelz 0 - ns oe* to high z toehz 0 6 ns sram write cycle parameter sym conditions min typ max units write cycle twc 15 - ns gw* pulse width tgw 10 - ns address setup to gw taswe 10 - ns address hold from gw tahwe 0 - data setup tds 7 - ns data hold tdh 0 - ns sram read cycle rama 0:17 ce 0:1 oe* ramd 0:15 tav trc toh toea toelz toehz sram write cycle rama 0:17 ce 0:1 oe* ramd 0:15 tds twc tdh t aswe tahwe tgw gw*
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 53 of 55 sram write cycle parameter sym conditions min typ max units pulse width tpw 2 ms data[n] to data[n+1] tpp 2 ms data[n] to data[n] tpd 16 ms led_ ln[7:0] led_data7 led_data6 led_data5 led_data4 led_data3 led_data2 led_data1 led_data0 tpw tpp tpd
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 54 of 55 tx application termination please contact altima communications inc. for the latest component value recommendation ac108rx txon txop ibref rxip rxin 1 tx+ 2 tx- 3 rx+ 4 unused 5 unused 6 rx- 7 unused 8 unused rj45 txc_p tx+_p tx-_p rx+_p rx-_p rxc_p txc_s tx+_s tx-_s rx+_s rx-_s rxc_s transformer 3.3v chassis gnd 75 w x 4 110 w 1% 49.9 w 1% 49.9 w 1% 0.1 m f 0.1 m f 10 k w 1% 1000 pf 3 kv
ac108 rm/ru/rn ultra low power 10/100 bridged repeater 2055 gateway parkway suite 700 , san jose, ca 95110 ( 408) 453-3700 (www.altimacom.com) altima communications inc. reserves the right to make changes to this document without notice. document revision 3.0 page 55 of 55 fx application termination please contact altima communications inc. for the latest component value recommendation to enable the fx mode, fx_sel7 pin must be pulled high by a 1 k w resistor. sdp sdn fxrn fxrp fxtp fxtn fx_sel7 1 rxvee 2 rxvcc 3 sd 4 rd- 5 rd+ 6 txvcc 7 txvee 8 nc 9 td+ 10 td- hfbr-5903 3.3v 1 k w ac108rx 2 k w 82 w 130 w 130 w 182 w 69.8 w 1.3 k w 130 w 69.8 w 100 w 1 uhl 1 uhl 0.1 uf 0.1 uf 0.1 uf 10 uf 182 w

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